| Lesson | Topic | Reading | Assigned | Due |
|---|---|---|---|---|
| L1 | Intro, Entity and architecture, Digital Systems Design | 1.1-1.7 | HW #1 | BOC L2 for T1A; BOC L3 for M6A |
| L2 | Digital Systems, hierarchical design, testbench | 2.1, 2.2.1, 2.2.2 | HW #2 | 0730 T3 for both M6A and T1A |
| L3 | Combinational elements, unsigned, constraints file, synthesis | 3.5.4, 4.2.3, 4.3.1 | HW #3 |
BOC L4 |
| L4 | Sequential elements | 5.1, 5.2, 5.7, 5.8 | HW #4 | BOC L5 |
| L5 | Combinations of elements, lab intro | 7.2 | HW #5 | BOC L6 |
| L6 | Lab1 - VGA Synchronization | Gate Check 1 | COB L6 | |
| L7 | Lab1 - VGA Synchronization | Gate Check 2 | COB L7 | |
| L8 | Lab1 - VGA Synchronization | Lab1 Functionality | COB L8 | |
| L9 | Finite State Machines | 10.2.1, 10.3.2, 10.4, 10.6.1 | Lab1 Write-up HW #6 |
COB L9 BOC L10 |
| L10 | Datapath and Control | 11.1, 11.2, 14.4.2 | HW #7 | BOC L11 |
| L11 | Datapath and Control | 11.5 | HW #8 | BOC L12 |
| L12 | Datapath and Control | HW #8b2 | BOC L13 | |
| L13 | Lab2 - Data acquisition, storage and display | Gate Check 1 | ||
| L14 | Lab2 - Data acquisition, storage and display | Gate Check 2 | ||
| L15 | Lab2 - Extra lesson added this year | Gate Check 3 | COB L15 | |
| L16 | Lab2 - Data acquisition, storage and display | Lab2 Functionality | COB L16 | |
| L17 | GR #1 | |||
| L18 | Soft CPU | Lab2 Write-up HW #9 |
COB L18 BOC L19 | |
| L19 | Soft CPU | HW #10 | BOC L20 | |
| L20 | Soft CPU | HW #11 | BOC L21 | |
| L21 | Lab3 - O'scope control | Final Project Ideas |
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| L22 | Lab3 - O'scope control | Gate Check 1 | BOC L22 | |
| L23 | SNOW DAY | |||
| L24 | Lab3 - O'scope control | Gate Check 2 | BOC L24 | |
| L25 | Lab3 - O'scope control | Gate Check 3 | COB L25 | |
| L26 | Lab3 - O'scope control | Lab 3 Functionality | COB L26 | |
| L27 | Direct Digital Synthesis | Final Project Ideas |
Lab3 Write-up Final Project Proposal Section 1 HW #12 |
COB L27 BOC L28 BOC L28 |
| L28 | Direct Digital Synthesis | HW #13 | BOC L29 | |
| L29 | Lab4 - Function generator | Gate Check 1 | COB L29 | |
| L30 | Lab4 - Function generator | Gate Check 2 Revised Final Project Proposal |
COB L30 BOC L30 | |
| L31 | Lab4 - Function generator | Lab4 Functionality | COB L31 | |
| L32 | GR #2 | |||
| L33 | Lab5 - Final Project Work on Final Project Plan and Design |
Lab4 write-up |
BOC L33 | |
| L34 | Lab5 - Final Project Milestone #1 |
Final Project Plan Section 2 |
BOC L34 | |
| L35 | Lab5 - Final Project Milestone #2 |
Milestone#1 | BOC L35 | |
| L36 | Lab5 - Final Project Milestone #2 |
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| L37 | Lab5 - Final Project | Milestone#2 | BOC L37 | |
| L38 | Lab5 - Final Project Final push |
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| L39 | Lab5 - Final Project Final push |
Functionality Due | COB L39 | |
| L40 | Final Presentations | Project Write-up Final Presentation |
BOC L40 BOC L40 |