ECE383
Start date: March 22
End date: April 4
Lab: 4
Status Complete

Lab 4 - Function generation

The goal of this lab is to generate an audio waveform with a high degree of accuracy in both its period and frequency.

Lab Overview

You are to use Direct Digital Synthesis to reproduce your audio waveform. For required functionality your system should create a sinusoid. For B-Level functionality, you must create a different waveform on the other channel. You may choose any waveform so long as its not Piecewise Linear. A few interesting examples would be the sinc function, exponentially damped sinusoids, or a waveform from a musical instrument (guitar, piano, or clarinet). It is your responsibility to get the samples for this waveform. I would suggest either deriving the waveform using a program like Python, Java, Matlab, or using a spreadsheet. Here is an example spreadsheet to create the BRAM initialization text for a 1024 entry LUT SineWaveLUT_1024.xlsx which you would need to modify for your size LUT. Here is a MATLAB example: BRAM_LUT.m and a JAVA example: BRAM_code.java Consult the handout associated with lesson 27 for more details on how to accomplish this. These 3 examples also create an unsigned sine LUT, not a signed LUT, which you might want to modify.

Requirements

While you have the flexibility to design the waveform generator as you see fit, your system must meet the following requirements:
  1. Use an update rate of 48kHz
  2. Your function generator should be able to create a maximum frequency of 12000 Hz.
  3. Your function generator should be able to create a minimum frequency between a 0.5 Hz and 1.0 Hz (this is also the minimum change in frequency).
  4. When your phase increment X = 1.0, the output frequency should be 200 Hz +/- 20 Hz.
  5. Be able to generate a full amplitude waveform on your lab2 o'scope display.
  6. Only one BRAM may be used for each channel.
  7. A FSM must be used to control the datapath. (using FSM coding style taught in lesson 9)
  8. Microblaze is not required, but may be used if desired in place of the FSM.

Hardware

You will have to create the block diagram for your lab4 function generator and upload it to bitbucket for milestone 1. Your design must be segregated into a lab4 datapath and a lab4 control unit, and will need your lab2 control unit and a modified lab2 datapath. Your design must show the all the needed BBB design blocks in the lab4 datapath, the states in the FSM, the control word, and the status word joining the datapath and control unit. All bus widths and Q formats for registers must be shown. This diagram must be neat and readable.
  • Here is a draft of the top_level lab4 block diagram, Lab4_Block_Diagram, and a draft of a portion of the example Lab4_datapath block diagram, Interpolation Block Diagram you can use as a starting point.

    The final value for your left (un-interpolated) and right (interpolated) signal you generate will be connected to the Codec's L_Bus_in and R_Bus_in (signed values) so you can listen to the output tones using ear-buds or a speaker, and will also be sent to your Lab2 O'Scope, so a good insertion point would be where your lab2 datapath receives the L_Bus_Out and R_Bus_Out (signed values). Since you created an O'Scope in Lab2, you will use this to see your output signal on your monitor. Since your lab4 FSM and lab4 datapath will need the Audio_Codec_Wrapper (with Clock_Wiz_1) and "Ready" signal from Lab2, put your Lab4 FSM and Lab4 datapath inside your lab2 block diagram (see Lab4_Block_Diagram). Therefore, you will also turn in a modified Lab2 block diagram showing the interface to the Lab4 FSM and Lab4 datapath for milestone 1. So you can easily test if your lab2 is working, switch(2) will be used to select lab2or4, for lab2 selecting the audio codec L_bus_out and R_bus_out as inputs, and for lab4 selecting your uninterpolated and interpolated signals to send to the Lab2 video.

    For lab4, you will use switch(5:4) to select 4 pre-calulated phase-increments (see milestone 1) for 4 output frequencies (see Interpolation Block Diagram ):

    Also for lab4,

    Signed Multiplication with Unsigned Data: Our VHDL multiplier does signed multiplication, not unsigned multiplication. It assumes the numbers being multiplied are signed, not unsigned. (For example, if the two numbers being multiplied have a '1' in the MSB, it assumes they are negative and produces a positive result, with a '0' in the MSB. So, if your two numbers were really intended to be unsigned positive numbers, you might get the wrong result).

    So the interpolation data flow show in the block diagram linked above, the flow is assumed to be signed values, and it is assumed your BRAM has stored your sine LUT as signed values. Therefore, if you created your BRAM sine LUT with 16-bit unsigned values, after your read out these BRAM values, you will first need to convert them to signed values, doing something like this:

    For your interpolator datapath block diagram, be sure to know if your BRAM LUT is composed of 16-bit signed values or 16-bit unsigned values, and add a conversion block if needed.

    Looking at the data flow going into the two multipliers, the above ensured NEXT and BASE are signed. However, OFFSET and the AMPLIFY_SWITCHES are unsigned.
  • We need to fool the signed multiplier into treating OFFSET and the AMPLIFY_SWITCHES as a signed number. Signed numbers are only negative when the MSb is a "1". If the MSb is a '0', it is positive, it is unsigned. Therefore, you need to append a '0' to the MSb of OFFSET and the AMPLIFY_SWITCHES before the multiply, which ensures the answer will be correct, and then there will be an extra MSb in the answer you should delete. The final answer your send to the audio codec or to your lab2 o'scope should be 18-bits, so you will also truncate off the lower bits you do not need.
  • Another reason to do the amplification while the data is still SIGNED, is amplifying a signed value gets bigger about zero (or your x-axis calibrated about row 220 on your scopeface). If you instead were to amplify UNSIGNED data, it will not grow centered on row 220.

    Required Functionality

    Use switch(5:4) to demonstrate your system can generate the 4 different frequencies. For required functionality, Interpolation between the output samples is not required. The waveform should be played back through the Audio Codec interface on the left channel producing an audible tone on a speaker and the appropriate waveform should be displayed on your lab2 scopeface monitor. Remember to wait for the ready signal.

    B-level Functionality

  • Switch(7:6) must be able to amplify or attenuate the signal to 4 different amplification levels. The signal must be equally amplified about the DC axis (row = 220).

    For B-level Functionality interpolation between the output samples is not required.

    A-level Functionality

    Modify the hardware for the right channel to interpolate between samples using (base + (next-base)*offset) method. You must create the Interpolated signal (for channel 2), you also must create the un-interpolated signal (for channel 1), so you can compare ch1 and ch2 to see the difference (and include an image of your scopeface monitor showing this difference). This does NOT require duplicate hardware, since in calculating the interpolated signal, you also already create the un-interpolated signal (known as BASE).  However, you will need the amplify BASE the same way you amplify the interpolated signal before if goes to channel 2. 

    You may swap A and B functionality if desired.

    Bonus Functionality

    Modify your design to continuously create a "chirp" signal, by continuously incrementing the phase increment (with an appropriate time delay  between increments), and demonstrate using a speaker. 

    Milestone 1

    At the COB of the day of the first lab session, you should have completed your design and uploaded it to bitbucket. This should include the mathematical analysis you did to meet the requirements in the "Requirements" section above, and answering the following questions.
    (0) Given the mathematical analysis you did to meet the requirements in the "Requirements" section above, what is the Q format required for your index.offset register (like Qxx.xx)? Given this Q format, answer and show calculations for the following questions:
    (1) phase increment needed for the maximum frequency of 12,000 Hz. Give this answer in decimal and in binary in the proper Q format.
    (2) the size of the BRAM buffer needed, assuming it contains one cycle of a sinusoid
    (3) the minimum frequency produced
    (4) the frequency produced when your phase increment is 1.0
    (5) the phase increment value that gets you closest to 440Hz. Give the answer in both decimal and in binary Q format.
    (6) what that closest frequency to 440 Hz is that you can create.
    [Hint: we did these calculations in the last slides for Lesson 26] To determine the frequency of your signals on the scopeface monitor, we need to know what the time axis is for the lab2 O'scope you created. [Remember: frequency = 1/(period of one cycle)] You are filling your lab2 BRAM at a rate of 48KHz, so each scopeface pixel (or column count) corresponds in time to 1/(48 kHz) = 20.8333333 micro-seconds. You are drawing the wave from column 20 to 620, or 600 pixels.
    (7) how long in time do these 600 pixels represent?
    Your scopeface grid should have 10 major grid blocks, each with a width of 60 pixels.
    (8) how long in time do these grid blocks represent?
    (9) If your function generate creates a sine wave such that exactly two cycles of the sinewave fit on your scopeface (ie., across 600 pixels), what is the frequency of this sine wave?
    (10) What must your phase increment be to generate this sine wave?
    You should also include the hardware block diagram design and the State Machine design for the items listed in the "Hardware" section above [the lab4 and modified lab3 block diagrams]. The block diagrams must look professional and not sloppy.
    (11)The datapath for the lab4 interpolation hardware.
    (12) The FSM state transition diagram and CW output table
    (13) The overall top-level lab4 block diagram modified from the old lab2 diagram, showing blocks for the lab4 datapath, lab4 FSM, and how they interact with the remaining lab2 components.

    Milestone 2

    At the COB of the day of the second lab period, you should have a working testbench testing your lab4 interpolation hardware block diagram (with your BRAM LUT inside) and lab4 FSM. When simulating your design, you can have the testbench supply a mock system clock (100 MHz) and a mock ready signal (clock at 48 kHz) in place of the ready signal generated the Audio_Codec_Wrapper.

    You do not need to have your switches working for this test bench nor interfacing with your lab2 FSM or lab2 datapath.

    Have the testbench test the interpolation of at least four cases, two cases for positive NEXT and BASE and two cases for negative NEXT and BASE, and for each pair of cases hase one such that NEXT is greater than BASE and the other such that BASE is greater than NEXT. Also do a simulation that increases the amplitude and one that decreases the amplitude with the amplitude multiplier.

    When complete, I expect your timing diagram to contain at least: You need to describe in words and math what we are seeing in your simulation plot, to justify that your VHDL code is working (do not only include the plot with no description) For example, from a hypothetical plot
  • Note: the above plot is just a testbench testing the interpolation math. This plot is missing signals clk, reset, ready, FSM state, Phase increment, Index.Offset, BRAM address, BRAM data, which are also needed for Milestone 2.

    For Milestone 2, also describe your method for creating your BRAM look-up tables for your waveforms in your README, and upload any code (like spreadsheets or python code) used. Here is an example spreadsheet to create the BRAM initialization text for a 1024 entry LUT SineWaveLUT_1024.xlsx which you would need to modify for your size LUT.

    README

    The README writeup should include:

    Grading

    Item Points
    Milestone #1 15
    Milestone #2 15
    Required Functionality 30
    B Functionality 10
    A Functionality 10
    Bonus Functionality 5
    Use of Git / Bitbucket 5
    Code Style 5
    README 10
    Total 100